It is known that an FET (Field Effect Transistor) using a gallium nitride (GaN) based semiconductor has large current collapse and large leakage current. The crystal dislocation and crystal defect, which are one of the causes in an epitaxial crystal are mentioned.
Since the crystal defects degrades fundamental performances of the GaN based FETs, such as increase of leakage current, and generating of a current collapse phenomenon, it is dramatically important to obtain an epitaxial layer with little crystal defects.
In order to decrease the crystal dislocation and the crystal defect of a GaN epitaxial layer, inserting an aluminum gallium nitride (AlGaN) layer and an aluminum nitride (AlN) layer into a GaN layer is known.
As shown in FIG. 1, the configuration of the basic unit of the conventional high power semiconductor device, which is composed of a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, etc. includes a GaN layer 12 placed on the substrate 10 which is composed of SiC; an AlGaN layer 14 placed on the GaN layer 12; and a gate electrode 24, a source electrode 20, and a drain electrode 22 which are placed on the AlGaN layer 14.
Furthermore, as shown in FIG. 1, as for the conventional semiconductor device, the isolation region acting as a non-active area NA is formed in the periphery of an active area AA which is composed of the AlGaN layer 14, by using mesa etching technology, ion implantation technology, etc.
As shown in FIG. 1, the gate electrode 24, the source electrode 20, and the drain electrode 22 are connected to a gate terminal electrode 240, a source terminal electrode 200, and a drain terminal electrode 220 which are placed on the isolation region acting as the non-active area NA, respectively.
FIG. 2 shows a schematic section structure taken in the line I-I of FIG. 1, and is an example in which an isolation region 25 which acts as the non-active area NA in the periphery of the active area AA by mesa etching technology is formed. A source electrode contact 20a is placed between the source electrode 20 and the AlGaN layer 14, and a drain electrode contact 22a is placed between the drain electrode 22 and the AlGaN layer 14.
That is, as shown in FIG. 2, the isolation region 25 is formed by mesa etching of a part of the AlGaN layer 14 and the GaN layer 12 in the periphery of the AA area of the conventional semiconductor device. The active area AA of the semiconductor device is specified by the isolation region 25 formed by mesa etching. In addition, an insulating layer 30 acting as a passivation film is formed on the sidewall part of the isolation region 25 formed by mesa etching and the active area, as shown in FIG. 2.
As shown in FIG. 1, the conventional semiconductor device is electrically insulated between the gate and the drain by the isolation region acting as the non-active area NA except for the active area AA. For this reason, originally, an amount of surface leakage current does not flow between the gate and the drain on the isolation regions except for the active area AA.
However, when a great value of voltage is applied between the gate and drain, an electric field concentrates on the gate electrode tip region GP between the gate electrode 24 and the drain terminal electrode 220. For this reason, an amount of surface leakage current flows between the gate electrode 24 and the drain terminal electrode 220, and the characteristic degradation of a semiconductor device is caused. There is a problem of resulting in the breakdown of a semiconductor device depending on the case.
For example, since GaN and AlGaN or AlN have large lattice constant difference, and electric charges induced by piezoelectric polarization effect are generated between a GaN layer 12 and an AlGaN layer 14, there is problem that the electric charges generated in the GaN layer 12 will degrade a high frequency performance of a semiconductor device extremely.
The electric charges induced by such piezoelectric polarization effect becomes the cause of increasing the conductivity of the GaN layer 12, increasing leakage current between a gate electrode 24 and a source electrode 20 or between a gate electrode 24 and a drain electrode 22, and reducing the power amplification gain of a semiconductor device.
A field effect transistor using the GaN based semiconductor which can form a gate size in 0.1 micrometer class, and is not occurred leakage current between a gate electrode and a source electrode or a drain electrode, and a fabrication method for the same, are already disclosed (for example, refer to Patent Literature 1). In the Patent Literature 1, the gate leakage current is reduced by using the field effect transistor having a gate electrode in which the sectional shape is T shape.
Moreover, a high resistivity group III nitride semiconductor crystal, the group III nitride semiconductor substrate, and the semiconductor device, and a fabrication method of the group III nitride semiconductor crystal, are already disclosed (for example, refer to Patent Literature 2). In the Patent Literature 2, the Fe doped GaN layer, which is the group III nitride semiconductor crystal in which Fe is doped as transition metals, for example, and whose Ga atom vacancy density is not more than 1×1016 cm−3 is disclosed. The Fe atoms density of the Fe doped GaN layer is 5×1017 cm−3 to 5×1020 cm−3. Moreover, a semiconductor device which has the semiconductor layer formed on the group III nitride semiconductor substrate which is composed of the above-mentioned Fe doped GaN layer is also disclosed.
Moreover, it is already disclosed also about a semiconductor element which can perform multilayer formation of a plurality of nitride based compound semiconductor layers which have a difference of the lattice constant more than a predetermined value in the effective crystalline state, and can suppress propagation of the threading dislocations to an epitaxial growth direction (for example, refer to Patent Literature 3).
In the high power semiconductor device which is composed of a GaN layer, an AlGaN layer, etc., when electrical isolation is performed by the ion implantation (implanted isolation) technology, there is a problem that the reliability of the power semiconductor device decreases to a low value.
On the other hand, in the high power semiconductor device which is composed a GaN layer, an AlGaN layer, etc., since a step is made to a device in the electrical isolation method by mesa etching, there is a problem that a focus becomes difficult to match when forming wiring etc. with an exposure device, and it becomes difficult to perform a miniaturization.